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HI5731
TM
Data Sheet
May 2000
File Number
4070.6
12-Bit, 100 MSPS, High Speed D/A Converter
The HI5731 is a 12-bit, 100 MSPS, D/A converter which is implemented in the Intersil BiCMOS 10V (HBC-10) process. Operating from +5V and -5.2V, the converter provides -20.48mA of full scale output current and includes an input data register and bandgap voltage reference. Low glitch energy and excellent frequency domain performance are achieved using a segmented architecture. The digital inputs are TTL/CMOS compatible and translated internally to ECL. All internal logic is implemented in ECL to achieve high switching speed with low noise. The addition of laser trimming assures 12-bit linearity is maintained along the entire transfer curve.
Features
* Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . 100 MSPS * Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .650mW * Integral Linearity Error . . . . . . . . . . . . . . . . . . . . 0.75 LSB * Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . .3.0pV-s * TTL/CMOS Compatible Inputs * Improved Hold Time . . . . . . . . . . . . . . . . . . . . . . . . 0.25ns * Excellent Spurious Free Dynamic Range
Applications
* Cellular Base Stations * GSM Base Stations * Wireless Communications
Ordering Information
PART NUMBER HI5731BIP HI5731BIB HI5731-EVS TEMP. RANGE (oC) -40 to 85 -40 to 85 25 PACKAGE 28 Ld PDIP 28 Ld SOIC PKG. NO. E28.6 M28.3
* Direct Digital Frequency Synthesis * Signal Reconstruction * Test Equipment * High Resolution Imaging Systems * Arbitrary Waveform Generators
Evaluation Board (SOIC)
Pinout
HI5731 (PDIP, SOIC) TOP VIEW
D11 (MSB) 1 D10 2 D9 3 D8 4 D7 5 D6 6 D5 7 D4 8 D3 9 D2 10 D1 11 D0 (LSB) 12 NC 13 NC 14 28 DGND 27 AGND 26 REF OUT 25 CTRL OUT 24 CTRL IN 23 RSET 22 AVEE 21 IOUT 20 IOUT 19 ARTN 18 DVEE 17 DGND 16 DVCC 15 CLOCK
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000
HI5731 Typical Application Circuit
+5V 0.01F DVCC (16) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 (MSB) (1) D10 (2) D9 (3) D8 (4) D7 (5) D6 (6) D5 (7) D4 (8) D3 (9) D2 (10) D1 (11) D0 (LSB) (12) CLK (15) 50 DGND (17, 28) 64 (20) IOUT (23) RSET 976 (19) ARTN (27) AGND (21) IOUT 64 D/A OUT (26) REF OUT -5.2V (AVEE) (24) CTRL IN (25) CTRL OUT 0.1F HI5731
DVEE (18) 0.1F 0.01F - 5.2V (DVEE)
(22) AVEE 0.01F - 5.2V (AVEE) 0.1F
Functional Block Diagram
(LSB) D0 D1 D2 D3 D4 D5 D6 D7 D8 15 D9 D10 (MSB) D11 REF CELL CLK OVERDRIVEABLE VOLTAGE REFERENCE AVEE AGND DVEE DGND DVCC REF OUT RSET + 25 CTRL OUT CTRL IN UPPER 4-BIT DECODER 15 15 SWITCHED CURRENT CELLS IOUT IOUT 12-BIT MASTER REGISTER DATA BUFFER/ LEVEL SHIFTER SLAVE REGISTER 227 227 8 LSBs CURRENT CELLS
R2R NETWORK ARTN
-
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HI5731
Absolute Maximum Ratings
Digital Supply Voltage VCC to DGND . . . . . . . . . . . . . . . . . . . +5.5V Negative Digital Supply Voltage DVEE to DGND . . . . . . . . . . -5.5V Negative Analog Supply Voltage AVEE to AGND, ARTN . . . . . -5.5V Digital Input Voltages (D11-D0, CLK) to DGND. . . . . DVCC to -0.5V Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . 2.5mA Voltage from CTRL IN to AVEE . . . . . . . . . . . . . . . . . . . . 2.5V to 0V Control Amplifier Output Current . . . . . . . . . . . . . . . . . . . . . 2.5mA Reference Input Voltage Range . . . . . . . . . . . . . . . . . .-3.7V to AVEE Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature HI5731BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVEE , DVEE = -4.94 to -5.46V, VCC = +4.75 to +5.25V, VREF = Internal TA = 25oC for All Typical Values HI5731BI TA = -40oC TO 85oC
PARAMETER SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL Differential Linearity Error, DNL Offset Error, IOS Full Scale Gain Error, FSE Offset Drift Coefficient Full Scale Output Current, IFS Output Voltage Compliance Range DYNAMIC CHARACTERISTICS Throughput Rate Output Voltage Full Scale Step Settling Time, tSETT , Full Scale Singlet Glitch Area, GE (Peak) Doublet Glitch Area, (Net) Output Slew Rate Output Rise Time Output Fall Time Spurious Free Dynamic Range within a Window (Note 3) (Note 3) (Note 3)
TEST CONDITIONS
MIN 12
TYP 0.75 0.5 20 1 20.48 20 5 3 1,000 675 470 85 77 75 80 78 79 70 70 69 -1.23 175 -
MAX 1.5 1.0 75 10 0.05 0 -1.17 +50
UNITS Bits LSB LSB A % A/oC mA V MSPS ns pV-s pV-s V/s ps ps dBc dBc dBc dBc dBc dBc dBc dBc dBc V V/oC A
(Note 4) ("Best Fit" Straight Line) (Note 4) (Note 4) (Notes 2, 4) (Note 3)
-1.25 100 -1.27 -125
To 0.5 LSB Error Band RL = 50 (Note 3) RL = 50 (Note 3) RL = 50, DAC Operating in Latched Mode (Note 3) RL = 50, DAC Operating in Latched Mode (Note 3) RL = 50, DAC Operating in Latched Mode (Note 3) fCLK = 10 MSPS, fOUT = 1.23MHz, 2MHz Span fCLK = 20 MSPS, fOUT = 5.055MHz, 2MHz Span fCLK = 40 MSPS, fOUT = 16MHz, 10MHz Span fCLK = 50 MSPS, fOUT = 10.1MHz, 2MHz Span fCLK = 80 MSPS, fOUT = 5.1MHz, 2MHz Span fCLK = 100 MSPS, fOUT = 10.1MHz, 2MHz Span
Spurious Free Dynamic Range to Nyquist (Note 3)
fCLK = 40 MSPS, fOUT = 2.02MHz, 20MHz Span fCLK = 80 MSPS, fOUT = 2.02MHz, 40MHz Span fCLK = 100 MSPS, fOUT = 2.02MHz, 50MHz Span
REFERENCE/CONTROL AMPLIFIER Internal Reference Voltage, VREF Internal Reference Voltage Drift Internal Reference Output Current Sink/Source Capability (Note 4) (Note 3) (Note 3)
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HI5731
Electrical Specifications
AVEE , DVEE = -4.94 to -5.46V, VCC = +4.75 to +5.25V, VREF = Internal TA = 25oC for All Typical Values (Continued) HI5731BI TA = -40oC TO 85oC PARAMETER Internal Reference Load Regulation Input Impedance at REF OUT pin Amplifier Large Signal Bandwidth (0.6VP-P) Amplifier Small Signal Bandwidth (0.1VP-P) Reference Input Impedance Reference Input Multiplying Bandwidth (CTL IN) DIGITAL INPUTS (D9-D0, CLK, INVERT) Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Input Logic Current, IIH Input Logic Current, IIL Digital Input Capacitance, CIN TIMING CHARACTERISTICS Data Setup Time, tSU Data Hold Time, tHLD Propagation Delay Time, tPD CLK Pulse Width, tPW1, tPW2 POWER SUPPLY CHARACTERISTICS IEEA IEED ICCD Power Dissipation Power Supply Rejection Ratio NOTES: 2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 1.28mA). Ideally the ratio should be 16. 3. Parameter guaranteed by design or characterization and not production tested. 4. All devices are 100% tested at 25oC. 100% production tested at temperature extremes for military temperature devices, sample tested for industrial temperature devices. 5. Dynamic Range must be limited to a 1V swing within the compliance range. (Note 4) (Note 4) (Note 4) (Note 4) VCC 5%, VEE 5% 42 70 13 650 5 50 85 20 mA mA mA mW A/V See Figure 1 (Note 3) See Figure 1 (Note 3) See Figure 1 (Note 3) See Figure 1 (Note 3) 3.0 0.5 3.0 2.0 0.25 4.5 ns ns ns ns (Note 4) (Note 4) (Note 4) (Note 4) (Note 3) 2.0 3.0 0.8 400 700 V V A A pF (Note 3) Sine Wave Input, to Slew Rate Limited (Note 3) Sine Wave Input, to -3dB Loss (Note 3) (Note 3) RL = 50, 100mV Sine Wave, to -3dB Loss at IOUT (Note 3) TEST CONDITIONS IREF = 0 to IREF = -125A MIN TYP 50 1.4 3 10 12 200 MAX UNITS V k MHz MHz k MHz
Timing Diagrams
CLK 50%
V D11-D0
GLITCH AREA = 1/2 (H x W)
HEIGHT (H) 1/2 LSB ERROR BAND
IOUT WIDTH (W) tSETT tPD t(ps)
FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM
FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT METHOD
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HI5731 Timing Diagrams
(Continued)
tPW1 tPW2
CLK
50%
tSU tHLD D11-D0
tSU tHLD
tSU tHLD
tPD
IOUT
tPD
tPD
FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
Typical Performance Curves
680 CLOCK FREQUENCY DOES NOT ALTER POWER DISSIPATION 640 (mW) (V) 600 560 -50 -30 -10 10 30 50 70 90
-1.21
-1.23
-1.25
-1.27
-1.29 -50 -30 -10 10 30 50 70 90
TEMPERATURE
TEMPERATURE
FIGURE 4. TYPICAL POWER DISSIPATION OVER TEMPERATURE
FIGURE 5. TYPICAL REFERENCE VOLTAGE OVER TEMPERATURE
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HI5731 Typical Performance Curves
1.5 0.8
(Continued)
0.5 (LSB)
0.4
(LSB) 1.5 0 600 1200 1800 2400 3000 3600 4200
0.0
-0.5 -0.4
-0.8 400 1000 1600 2200 CODE 2800 3400 4000
CODE
FIGURE 6. TYPICAL INL
FIGURE 7. TYPICAL DNL
ATTEN 20dB RL -10.0dBm 28
10dB/
MKR -87.33dB -73kHz fC = 10 MSPS
24
(A)
20
S
16
12 -40 -20 -0 20 40 60 80 100
C CENTER 1.237MHz SPAN 2.000MHz
TEMPERATURE
FIGURE 8. OFFSET CURRENT OVER TEMPERATURE
FIGURE 9. SPURIOUS FREE DYNAMIC RANGE = 87.3dBc
ATTEN 20dB RL -10.0dBm
10dB/
MKR -76.16dB -53kHz fC = 20 MSPS
ATTEN 20dB RL -10.0dBm
10dB/
MKR -75.17dB -70kHz fC = 40 MSPS
S
C CENTER 5.055MHz SPAN 2.000MHz
C
CENTER 16.00MHz
SPAN 10.00MHz
FIGURE 10. SPURIOUS FREE DYNAMIC RANGE = 76.16dBc
FIGURE 11. SPURIOUS FREE DYNAMIC RANGE = 75.17dBc
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HI5731 Typical Performance Curves
ATTEN 20dB RL -10.0dBm
(Continued)
10dB/
MKR -81.67dB -953kHz fC = 50 MSPS
ATTEN 20dB RL -10.0dBm
10dB/
MKR -77.00dB -93kHz fC = 80 MSPS
S
C CENTER 10.100MHz SPAN 2.000MHz
C CENTER 5.097MHz SPAN 2.000MHz
FIGURE 12. SPURIOUS FREE DYNAMIC RANGE = -81.67dBc
FIGURE 13. SPURIOUS FREE DYNAMIC RANGE = 77dBc
ATTEN 20dB RL -10.0dBm
10dB/
MKR -85.60dB -33kHz fC = 100 MSPS
ATTEN 20dB RL -10.0dBm
10dB/
MKR -85.50dB 73kHz fC = 100 MSPS
S
S
C CENTER 2.027MHz SPAN 2.000MHz
C
CENTER 5.000MHz
SPAN 2.000MHz
FIGURE 14. SPURIOUS FREE DYNAMIC RANGE = -85.60dBc
FIGURE 15. SPURIOUS FREE DYNAMIC RANGE = 85.5dBc
ATTEN 20dB RL -10.0dBm
10dB/
MKR -80.50dB -807kHz fC = 100 MSPS
ATTEN 20dB RL -10.0dBm
10dB/
MKR -72.17dB -467kHz fC = 100 MSPS
S
C CENTER 10.133MHz SPAN 2.000MHz CENTER 26.637MHz SPAN 2.000MHz
FIGURE 16. SPURIOUS FREE DYNAMIC RANGE = 80.5dBc
FIGURE 17. SPURIOUS FREE DYNAMIC RANGE = 72.17dBc
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HI5731 Typical Performance Curves
ATTEN 20dB RL -10.0dBm 10dB/
(Continued)
MKR -71.16dB 2.99MHz fC = 40 MSPS fO = 2.02MHz ATTEN 20dB RL -10.0dBm MKR -70.50dB 1.98MHz fC = 80 MSPS fO = 2.02MHz
10dB/
S
S
C
C
START FREQUENCY 500kHz
STOP FREQUENCY 20MHz
START FREQUENCY 500kHz
STOP FREQUENCY 40MHz
FIGURE 18. SPURIOUS FREE DYNAMIC RANGE = 71.16dBc
ATTEN 20dB RL -10.0dBm
FIGURE 19. SPURIOUS FREE DYNAMIC RANGE = 70.5dBc
MKR -70.00dB 4.13MHz fC = 100 MSPS fO = 2.02MHz
10dB/
S
C
START FREQUENCY 500kHz
STOP FREQUENCY 50MHz
FIGURE 20. SPURIOUS FREE DYNAMIC RANGE = 70dBc
Pin Descriptions
PIN NUMBER 1-12 15 13, 14 16 17, 28 18 23 27 19 21 20 22 24 25 26 PIN NAME PIN DESCRIPTION D11 (MSB) thru Digital Data Bit 11, the Most Significant Bit thru Digital Data Bit 0, the Least Significant Bit. D0 (LSB) CLK NC DVCC DGND DVEE RSET AGND ARTN IOUT IOUT AVEE CTRL IN CTRL OUT REF OUT Data Clock Pin DC to 100 MSPS. No Connect. Digital Logic Supply +5V. Digital Ground. -5.2V Logic supply. External resistor to set the full scale output current. IFS = 16 x (VREF OUT / RSET). Typically 976. Analog Ground supply current return pin. Analog Signal Return for the R/2R ladder. Current Output Pin. Complementary Current Output Pin. -5.2V Analog Supply. Input to the current source base rail. Typically connected to CTRL OUT and a 0.1F capacitor to AVEE . Allows external control of the current sources. Control Amplifier Out. Provides precision control of the current sources when connected to CTRL IN such that IFS = 16 x (VREF OUT / RSET). -1.23V (Typ) bandgap reference voltage output. Can sink up to 125A or be overdriven by an external reference capable of delivering up to 2mA.
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HI5731 Detailed Description
The HI5731 is a 12-bit, current out D/A converter. The DAC can convert at 100 MSPS and runs on +5V and -5.2V supplies. The architecture is an R/2R and segmented switching current cell arrangement to reduce glitch. Laser trimming is employed to tune linearity to true 12-bit levels. The HI5731 achieves its low power and high speed performance from an advanced BiCMOS process. The HI5731 consumes 650mW (typical) and has an improved hold time of only 0.25ns (typical). The HI5731 is an excellent converter for use in communications applications and high performance instrumentation systems.
ZO = 50 CLK RT = 50 HI5731 DAC
FIGURE 21. CLOCK LINE TERMINATION
Rise and Fall times and propagation delay of the line will be affected by the Shunt Terminator. The terminator should be connected to DGND.
Digital Inputs
The HI5731 is a TTL/CMOS compatible D/A. Data is latched by a Master register. Once latched, data inputs D0 (LSB) thru D11 (MSB) are internally translated from TTL to ECL. The internal latch and switching current source controls are implemented in ECL technology to maintain high switching speeds and low noise characteristics.
Noise Reduction
To reduce power supply noise, separate analog and digital power supplies should be used with 0.1F and 0.01F ceramic capacitors placed as close to the body of the HI5731 as possible on the analog (AVEE ) and digital (DVEE ) supplies. The analog and digital ground returns should be connected together back at the device to ensure proper operation on power up. The VCC power pin should also be decoupled with a 0.1F capacitor.
Decoder/Driver
The architecture employs a split R/2R ladder and Segmented Current source arrangement. Bits D0 (LSB) thru D7 directly drive a typical R/2R network to create the binary weighted current sources. Bits D8 thru D11 (MSB) pass thru a "thermometer" decoder that converts the incoming data into 15 individual segmented current source enables. This split architecture helps to improve glitch, thus resulting in a more constant glitch characteristic across the entire output transfer function.
Reference
The internal reference of the HI5731 is a -1.23V (typical) bandgap voltage reference with 175V/oC of temperature drift (typical). The internal reference is connected to the Control Amplifier which in turn drives the segmented current cells. Reference Out (REF OUT) is internally connected to the Control Amplifier. The Control Amplifier Output (CTRL OUT) should be used to drive the Control Amplifier Input (CTRL IN) and a 0.1F capacitor to analog VEE. This improves settling time by providing an AC ground at the current source base node. The Full Scale Output Current is controlled by the REF OUT pin and the set resistor (RSET). The ratio is: IOUT (Full Scale) = (VREF OUT /RSET) x 16, The internal reference (REF OUT) can be overdriven with a more precise external reference to provide better performance over temperature. Figure 22 illustrates a typical external reference configuration.
Clocks and Termination
The internal 12-bit register is updated on the rising edge of the clock. Since the HI5731 clock rate can run to 100 MSPS, to minimize reflections and clock noise into the part proper termination should be used. In PCB layout clock runs should be kept short and have a minimum of loads. To guarantee consistent results from board to board controlled impedance PCBs should be used with a characteristic line impedance ZO of 50. To terminate the clock line, a shunt terminator to ground is the most effective type at a 100 MSPS clock rate. A typical value for termination can be determined by the equation: RT = ZO , for the termination resistor. For a controlled impedance board with a ZO of 50, the RT = 50. Shunt termination is best used at the receiving end of the transmission line or as close to the HI5731 CLK pin as possible.
HI5731 (26) REF OUT -1.25V R -5.2V
FIGURE 22. EXTERNAL REFERENCE CONFIGURATION
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HI5731
Multiplying Capability
The HI5731 can operate in two different multiplying configurations. For frequencies from DC to 100kHz, a signal of up to 0.6VP-P can be applied directly to the REF OUT pin as shown in Figure 23.
HI5731 CTRL OUT CTRL IN
TABLE 1. CAPACITOR SELECTION fIN 100kHz >1MHz C1 0.01F 0.001F C2 1F 0.1F
0.01F AVEE
Also, the input signal must be limited to 1VP-P to avoid distortion in the DAC output current caused by excessive modulation of the internal current sources.
REF OUT VIN CIN (OPTIONAL) RSET
Outputs
The outputs IOUT and IOUT are complementary current outputs. Current is steered to either IOUT or IOUT in proportion to the digital input code. The sum of the two currents is always equal to the full scale current minus one LSB. The current output can be converted to a voltage by using a load resistor. Both current outputs should have the same load resistor (64 typically). By using a 64 load on the output, a 50 effective output resistance (ROUT) is achieved due to the 227 (15%) parallel resistance seen looking back into the output. This is the nominal value of the R2R ladder of the DAC. The 50 output is needed for matching the output with a 50 line. The load resistor should be chosen so that the effective output resistance (ROUT) matches the line resistance. The output voltage is: VOUT = IOUT x ROUT. IOUT is defined in the reference section. IOUT is not trimmed to 12 bits, so it is not recommended that it be used in conjunction with IOUT in a differential-to-single-ended application. The compliance range of the output is from 1.25V to 0V, with a 1VP-P voltage swing allowed within this range.
TABLE 2. INPUT CODING vs CURRENT OUTPUT INPUT CODE (D11-D0) 1111 1111 1111 IOUT (mA) -20.48 -10.24 0 IOUT (mA) 0 -10.24 -20.48
FIGURE 23. LOW FREQUENCY MULTIPLYING BANDWIDTH CIRCUIT
The signal must have a DC value such that the peak negative voltage equals -1.25V. Alternately, a capacitor can be placed in series with REF OUT if DC multiplying is not required. The lower input bandwidth can be calculated using the following formula:
1 C IN = -------------------------------------------. ( 2 ) ( 1400 ) ( f IN )
For multiplying frequencies above 100kHz, the CTRL IN pin can be driven directly as seen in Figure 24.
HI5731 CTRL OUT C2 200 VIN AVEE C1 CTRL IN 50
FIGURE 24. HIGH FREQUENCY MULTIPLYING BANDWIDTH CIRCUIT
1000 0000 0000 0000 0000 0000
The nominal input/output relationship is defined as:
V IN I OUT = ------------- . 80
Settling Time
The settling time of the HI5731 is measured as the time it takes for the output of the DAC to settle to within a 1/2 LSB error band of its final value during a full scale (code 0000... to 1111.... or 1111... to 0000...) transition. All claims made by Intersil with respect to the settling time performance of the HI5731 have been fully verified by the National Institute of Standards and Technology (NIST) and are fully traceable.
In order to prevent the full scale output current from exceeding 20.48mA, the RSET resistor must be adjusted according to the following equation:
16V REF -. R SET = ---------------------------------------------------------------------------------------------V IN ( PEAK ) I OUT (FULL SCALE) - ---------------------------- 80
The circuit in Figure 24 can be tuned to adjust the lower cutoff frequency by adjusting capacitor values. Table 1 below illustrates the relationship.
Glitch
The output glitch of the HI5731 is measured by summing the area under the switching transients after an update of the DAC. Glitch is caused by the time skew between bits of the incoming digital data. Typically, the switching time of digital inputs are asymmetrical meaning that the turn off time is
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HI5731
faster than the turn on time (TTL designs). Unequal delay paths through the device can also cause one current source to change before another. In order to minimize this, the Intersil HI5731 employes an internal register, just prior to the current sources, which is updated on the clock edge. Lastly, the worst case glitch on traditional D/A converters usually occurs at the major transition (i.e., code 2047 to 2048). However, due to the split architecture of the HI5731, the glitch is moved to the 255 to 256 transition (and every subsequent 256 code transitions thereafter). This split R/2R segmented current source architecture, which decreases the amount of current switching at any one time, makes the glitch practically constant over the entire output range. By making the glitch a constant size over the entire output range this effectively integrates this error out of the end application. In measuring the output glitch of the HI5731 the output is terminated into a 64 load. The glitch is measured at any one of the current cell carry (code 255 to 256 transition or any multiple thereof) throughout the DACs output range. The glitch energy is calculated by measuring the area under the voltage-time curve. Figure 26 shows the area considered as glitch when changing the DAC output. Units are typically specified in picoVolt-seconds (pV-s). buffered to create the bipolar offset current needed to generate the -2V output with all bits `off'. The output current must be converted to a voltage and then gained up and offset to produce the proper swing. Care must be taken to compensate for the voltage swing and error.
5k REF OUT (26) +
1/ CA2904 2
-
5k
+
1/ CA2904 2
-
60
0.1F HI5731
240 240
50 IOUT (21) + HFA1100
-
VOUT
FIGURE 27. BIPOLAR OUTPUT CONFIGURATION
Interfacing to the HSP45106 NCO-16
The HSP45106 is a 16-bit, Numerically Controlled Oscillator (NCO). The HSP45106 can be used to generate various modulation schemes for Direct Digital Synthesis (DDS) applications. Figure 28 shows how to interface an HI5731 to the HSP45106.
HI5731 (21) IOUT 64 100MHz LOW PASS FILTER SCOPE
Interfacing to the HSP45102 NCO-12
The HSP45102 is a 12-bit, Numerically Controlled Oscillator (NCO). The HSP45102 can be used to generate various modulation schemes for Direct Digital Synthesis (DDS) applications. Figure 29 shows how to interface an HI5731 to the HSP45102. This high level block diagram is that of a basic PSK modulator. In this example the encoder generates the PSK waveform by driving the Phase Modulation Inputs (P1, P0) of the HSP45102. The P1-0 inputs impart a phase shift to the carrier wave as defined in Table 2.
TABLE 3. PHASE MODULATION INPUT CODING
50
FIGURE 25. GLITCH TEST CIRCUIT
a (mV)
P1 0
GLITCH ENERGY = (a x t)/2
P0 0 1 0 1
PHASE SHIFT (DEGREES) 0 90 270 180
0 1
t (ns)
1
FIGURE 26. MEASURING GLITCH ENERGY
Applications
Bipolar Applications
To convert the output of the HI5731 to a bipolar 4V swing, the following applications circuit is recommended. The reference can only provide 125A of drive, so it must be 3-11
The data port of the HSP45102 drives the 12-bit HI5731 DAC which converts the NCO output into an analog waveform. The output filter connected to the DAC can be tailored to remove unwanted spurs for the desired carrier frequency. The controller is used to load the desired center frequency and control the HSP45102. The HI5731 coupled with the HSP45102 make an inexpensive PSK modulator with Spurious Free performance down to -76dBc.
HI5731 Definition of Specifications
Integral Linearity Error, INL, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. Differential Linearity Error, DNL, is the measure of the error in step size between adjacent codes along the converter's transfer curve. Ideally, the step size is 1 LSB from one code to the next, and the deviation from 1 LSB is known as DNL. A DNL specification of greater than -1 LSB guarantees monotonicity. Feedthru, is the measure of the undesirable switching noise coupled to the output. Output Voltage Full Scale Settling Time, is the time required from the 50% point on the clock input for a full scale step to settle within an 1/2 LSB error band. Output Voltage Small Scale Settling Time, is the time required from the 50% point on the clock input for a 100mV step to settle within an 1/2 LSB error band. This is used by applications reconstructing highly correlated signals such as sine waves with more than 5 points per cycle. Glitch Area, GE, is the switching transient appearing on the output during a code transition. It is measured as the area under the curve and expressed as a picoVolt-time specification (typically pV-s). Differential Gain, AV, is the gain error from an ideal sine wave with a normalized amplitude. Differential Phase, , is the phase error from an ideal sine wave. Signal to Noise Ratio, SNR, is the ratio of a fundamental to the noise floor of the analog output. The first 5 harmonics are ignored, and an output filter of 1/2 the clock frequency is used to eliminate alias products. Total Harmonic Distortion, THD, is the ratio of the DAC output fundamental to the RMS sum of the harmonics. The first 5 harmonics are included, and an output filter of 1/2 the clock frequency is used to eliminate alias products. Spurious Free Dynamic Range, SFDR, is the amplitude difference from a fundamental to the largest harmonically or non-harmonically related spur. A sine wave is loaded into the D/A and the output filtered at 1/2 the clock frequency to eliminate noise from clocking alias terms. Intermodulation Distortion, IMD, is the measure of the sum and difference products produced when a two tone input is driven into the D/A. The distortion products created will arise at sum and difference frequencies of the two tones. IMD can be calculated using the following equation:
20Log (RMS of Sum and Difference Distortion Products) IMD = ------------------------------------------------------------------------------------------------------------------------------------------------------ . ( RMS Amplitude of the Fundamental )
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HI5731
U2 33 MSPS CLK BASEBAND BIT STREAM ENCODER K9 C11 B11 C10 A11 F10 F9 F11 H11 G11 G9 J11 G10 D10 CONTROLLER VCC J10 K11 CLK MOD2 MOD1 MOD0 PMSEL DACSTRB SIN15 SIN14 SIN13 SIN12 SIN11 SIN10 SIN9 SIN8 SIN7 SIN6 SIN5 SIN4 SIN3 SIN2 SIN1 SIN0 L1 K3 L2 L3 L4 J5 K5 L5 K6 J6 J7 L7 L6 L8 K8 L9 L10 VCC 16 1 2 3 4 5 6 7 8 9 10 11 12 15 R4 50 U1 DVCC IOUT 21 FILTER R1 64 20 24 25 C2 C1 0.1F 0.01F -5.2V_A -5.2V_A R2 64 TO RF UP-CONVERT STAGE
ENPOREG ENOFREG ENCFREG ENPHAC ENTIREG INHOFR INITPAC INITTAC TEST PARSER BINFMT
D11 (MSB) D10 IOUT D9 D8 D7 CNTRL IN D6 D5 D4 CNTRL OUT D3 D2 D1 D0 (LSB) REF OUT CLK RSET ARET
26 R3 976 19
23
B8 A8 B6 B7 A7 C7 C6 A6 A5 C5 A4 B4 A3 A2 B3 A1 B10 B9 A10 E11 E9 VCC H10 K2 J2 V
CC
C15_MSB C4 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 A2 A1 A0 CS WR PACI OES OEC
28 DGND 17 DGND
COS15 COS14 COS13 COS12 COS11 COS10 COS9 COS8 COS7 COS6 COS5 COS4 COS3 COS2 COS1 COS0 TICO
C2 B1 C1 D1 E3 E2 E1 F2 F3 G3 G1 G2 H1 H2 J1 K1 B2
AVSS 27 18 -5.2V_D DVEE HI5731 AVEE 22 -5.2V_A
L1 -5.2V_D 10H -5.2V_A
L2 10H
HSP45106
FIGURE 28. MODULATOR USING THE HI5731 AND THE HSP45106 16-BIT NCO
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HI5731
TO RF UP-CONVERT STAGE
U2 U1 40 MSPS I CLK ENCODER Q 16 19 20 18 17 12 9 CONTROL BUS CONTROLLER 14 13 10 11 SCLK SD SFTEN# MSB/LSB# HSP45102 -5.2V_D 18 DVEE HI5731 L1 -5.2V_D L2 -5.2V_A 10H R4 50 CLK P1 P0 LOAD# TXFR# ENPHAC# SEL_L/M# OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 6 5 4 3 2 1 28 27 26 25 24 23 VCC 16 1 2 3 4 5 6 7 8 9 10 11 12 DVCC IOUT 21
FILTER R1 64 20 24 25 C2 C1 0.1F 0.01F R2 64
BASEBAND BIT STREAM
D11 (MSB) D10 IOUT D9 D8 D7 CNTRL IN D6 D5 CNTRL OUT D4 D3 D2 D1 D0 (LSB) REF OUT 15 CLK 28 DGND 17 DGND RSET
-5.2V_A -5.2V_A
26 23 R3 976
ARET
19
AVSS 27 AVEE 22 -5.2V_A
10H
FIGURE 29. PSK MODULATOR USING THE HI5731 AND THE HSP45102 12-BIT NCO
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HI5731 Die Characteristics
DIE DIMENSIONS: 161.5 mils x 160.7 mils x 19 mils METALLIZATION: Type: AlSiCu Thickness: M1 - 8kA, M2 - 17kA PASSIVATION: Type: Sandwich Passivation Undoped Silicon Glass (USG) + Nitride Thickness: USG - 8kA, Nitride - 4.2kA Total 12.2kA + 2kA SUBSTRATE POTENTIAL (POWERED UP): VEED
Metallization Mask Layout
HI5731
REF OUT AGND
D8
D9
D10
D11
DGND
CTRL OUT D7 CTRL IN D6
D5
RSET
AVEE D4 IOUT
D3
IOUT
D2 ARTN D1
D0
CLK
DVCC
DGND
DVEE
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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